Out-of-order microprocessors can provide improved computational performance by executing instructions in a sequence that is different from the order in the program, so that instructions are executed when their input data is available rather than waiting for the preceding instruction in the program to execute. In order to allow instructions to run out-of-order on a microprocessor it is useful to be able to rename registers used by the instructions. This enables the removal of “write-after-read” (WAR) dependencies from the instructions as these are not true dependencies. By using register renaming and removing these dependencies, more instructions can be executed out of program sequence, and performance is further improved. Register renaming is performed by maintaining a map of which registers named in the instructions (called architectural registers) are mapped onto the physical registers of the microprocessor. This map may be referred to as a “register renaming map.”
Due to there being a limited number of architectural registers, compilers cannot always keep all the program variables in registers and as a result some variables, which were stored in registers, may need to be saved to memory (usually to the program stack) to free up architectural registers. When the values of the variables are subsequently required, the values must be read back from the memory (e.g. the stack) into a register again. This reading from memory introduces a delay.
There are many situations where this problem of insufficient architectural registers may occur. For example, this problem may occur where there are more variables than architectural registers within a function (resulting in register spill) and/or when one function (the parent function) calls another function (the child function) and there are insufficient architectural registers for both the parent and child functions. Although one solution would be to increase the number of available architectural registers, this is typically not possible as it would change the size of the instruction set.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known methods of operating a processor.